一种1553B总线协议编解码器的设计研究  

Design of the Encoder and Decoder Based on the 1553B Bus Protocol

作　　者：杨勇 王占领[1,2] 张登福[2] 

机构地区：[1]解放军93594部队 [2]空军工程大学航空航天工程学院

出　　处：《电子器件》2016年第1期46-50,共5页Chinese Journal of Electron Devices

基　　金：国防科技重点实验室基金项目(9140C6001070801)

摘　　要：编解码器是1553B协议芯片中的重要组成部分。为了自主研发1553B总线协议的IP核,满足对1553B协议芯片的广泛需求,设计了基于1553B总线协议的编解码器。对编码器和解码器采用自顶向下和独立设计的方法,充分利用同步时钟方法,提高了可靠性,有效解决了数据间干扰和亚稳态问题。通过仿真验证,结果表明设计实现了编码与解码功能。最后在FPGA硬件平台上进行了实际调试,测试取得了良好的效果,结果符合设计要求。The encoder and decoder are the indispensable components of the 1553B bus protocol chip. In order to research the IP core of 1553B bus autonomously and meet the extensive demand for 1553B protocol chip. This article designs the encoder and decoder based on the 1553B bus protocol. Using the top-down and independent meth-ods and synchronization ways of designing the encoder and decoder,it improves the reliability and lessens the interference between the data efficiently,and resolves the metastability issue. After simulation and verification,the results indicate that the functions of encoder and decoder are all achieved. At last,the testing on the FPGA hardware platform achieves effective results,the results correspond with the design demand.

关 键 词：1553B总线 编解码器 FPGA VERILOG HDL 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]