3D叠层封装集成电路的芯片分离技术  

The Chip Seperation Technology of 3D Stacked Package IC

作　　者：林晓玲[1,2] 梁朝辉 温祺俊 

机构地区：[1]工业和信息化部电子第五研究所,广东广州510610 [2]电子元器件可靠性物理及其应用技术重点实验室,广东广州510610

出　　处：《电子产品可靠性与环境试验》2016年第2期36-40,共5页Electronic Product Reliability and Environmental Testing

摘　　要：3D叠层封装是高性能器件的一种重要的封装形式,其鲜明的特点为器件的物理分析带来了新的挑战。介绍了一种以微米级区域研磨法为主、化学腐蚀法为辅的芯片分离技术,包括制样方法及技术流程,并给出了实际的应用案例。该技术实现了3D叠层芯片封装器件内部多层芯片的逐层暴露及非顶层芯片中缺陷的物理观察分析,有助于确定最终的失效原因,防止失效的重复出现,对于提高集成度高、容量大的器件的可靠性具有重要的意义。3D stacked package is one of the important packages for high-performance devices,whose specificity brings new challenge to the physical analysis of devices. A chip separation technology based on the micro-level regional grinding method and chemical etching method is introduced, including its sample preparation method and technique process, and a practical application example is given. The chip separation technology realizes the exposure of the internal multilayer chip layer by layer and the physical analysis of the defects in the non-top chip of the 3D stacked chip packaging device, which is helpful to determine the ultimate failure cause and to prevent the duplication of the failure. Besides, it has important significance for improving the reliability of high integration and large capacity devices.

关 键 词：3D叠层封装 集成电路 芯片分离技术 区域研磨法 化学腐蚀法 

分 类 号：TN405[电子电信—微电子学与固体电子学]