高速双域乘法器设计及其应用  

Design and Application of High Speed Dual-Field Multiplier

作　　者：郑朝霞[1] 资义纯 田园[1] 吴浩[1] 

机构地区：[1]华中科技大学光学与电子信息学院,湖北武汉430074

出　　处：《微电子学与计算机》2016年第5期1-5,共5页Microelectronics & Computer

基　　金：湖北省重大项目(2015ACA063);中央高校基本科研业务费资助;HUST(2014TS041);深圳市技术创新计划(CYZZ20140829104843693)

摘　　要：双域乘法器在椭圆曲线密码学中具有重要意义,是构成双域模乘器的重要组件.考虑到双域乘法器的关键路径主要由GF(p)域决定;因此,在传统的基4Booth编码乘法器的基础上进行优化设计,改进部分积产生电路以及Wallace压缩电路,使其能够同时支持GF(p)域和GF(2 m)域.设计的双域乘法器在FPGA实现结果表明,双域乘法器比单独实现两个域面积减小16.9%;延时比单独的GF(p)域增加1.188ns.将设计的双域乘法器应用到模乘器,结果表明,该设计完成一次256bit的模乘操作比已有的在时间上节约了7.35%.Duaal-Field multiplier is the important component of Dual-Field Montgomery multiplier and has important meaning for elliptic curve cryptography. Considering that the critical path of Dual-Field multiplier depends on the GFfp） field, Partial product generating circuit and Wallace compressor circuit was optimized based on traditional radix-4 Booth encoder multiplier（GF（p）） to support both GF（p） and GF（2 m） field. The designed Dual-Field multiplier implemented on Ft^A shows that the area is decreased by 16. 9% compare to the separating implement. The delay is increased by 1. 188 ns than the traditional field GF（p）. The designed Dual-Field multiplier is applied to Montgomery multiplier. The time for 256 bit Montgomery multiplier of our design is reduced by 7. 35% than paper proposed.

关 键 词：双域乘法器 双域模乘 BOOTH编码 双域4-2压缩器 

分 类 号：TN47[电子电信—微电子学与固体电子学]