基于FPGA的虚拟FIFO改进设计  

Improved design of virtual FIFO based on FPGA

作　　者：张玉平[1] 叶圣江 

机构地区：[1]成都工业学院通信工程学院,成都611730 [2]成都盟升科技有限公司遥感事业部,成都611731

出　　处：《沈阳工业大学学报》2016年第3期298-303,共6页Journal of Shenyang University of Technology

基　　金：四川省教育厅基金资助项目(14ZA0288)

摘　　要：为了降低网络接口缓存设计的开发难度和复杂度,对现有基于FPGA的DDR2虚拟FIFO设计进行了改进.提出了以FPGA(EP4CGX150F672)为核心、DDR2(MT47H128M16RT-25E)为数据缓存、采用Qsys系统互联及IPCORE辅助搭建设计的改进方案,实现了DVB-IP分组TS流的快速缓存,平滑IP网络抖动,避免了数据码流丢失和延迟过大的问题.该设计方案在降低传统设计难度和复杂度的背景下,具有良好的存储器兼容性,同时具有系统资源丰富、容量大、成本低和开发周期短等优点,在众多DVB行业的设备中使用后效果良好.In order to reduce the development difficulty and complexity of network interface buffer design, the design of DDR2 virtual FIFO based on FPGA was improved. An improved scheme, which taking FPGA （EP4CGX150F672） as the core and DDR2 （MT47H128M16RT-25E） as the data cache, and adopting Qsys system interconnection and IPCORE auxiliary building design, was proposed. The fast cache of DVB-IP packet TS flow is realized, and the IP network jitter is smoothed. In addition, the loss of data code flow and the problem of too large delay can be avoided. Under the background of reducing the difficulty and complexity of traditional design, the proposed design scheme has good memory compatibility, possesses such advantages as rich system resources, large capacity, low cost and short development cycle, and exhibits good effect after being used for the numerous equipment in DVB industry.

关 键 词：现场可编程门阵列 双倍速率 先入先出队列 系统互联 知识产权核 网络抖动 码流 节目参考时钟 

分 类 号：TN914[电子电信—通信与信息系统]