一种新型的10G以太网并行循环冗余校验设计  

A New Design of Parallel Cyclic Redundancy Check for 10 Gigabit Ethernet

作　　者：钟桂森 易清明[1] 石敏[1] 

机构地区：[1]暨南大学信息科学技术学院,广州510632

出　　处：《计算机工程》2016年第5期292-296,303,共6页Computer Engineering

基　　金：广东省科技计划基金资助项目(2013B090800022);广东省工程技术研究中心基金资助项目(2012gczxA003)

摘　　要：现有10G以太网中的循环冗余校验(CRC)编译码器不能同时兼顾计算速度与资源占用,为此,设计一种新型的10G以太网并行CRC编译码器。编码时,通过编码预处理解决不定长字节带来的CRC编码问题,简化CRC编码电路的设计。译码时,通过译码预处理分离出以太网帧的帧校验序列(FCS)域,恢复编码预处理模块输出的数据,简化CRC校验电路的设计。在实现CRC编码校验时对传统的异或运算电路进行优化,降低运算电路门延时,提高运算速度,并能自动切换CRC编码校验方法以兼容现有以太网。实验结果表明,与其他3种方法相比,该方法占用逻辑资源少,计算速度快,可实现实时性输出,同时满足10G以太网156.25 MHz的时序要求。According to the problem that the existing parallel Cyclic Redundancy Check（CRC） codec for 10 Gigabit Ethernet cannot take into account both computing speed and resource usage, a new type of parallel CRC codec for 10 Gigabit Ethernet is designed. Encoding preprocessing can easily solve the problem of the CRC encoding brought by variable length byte,so that the CRC encoding circuit can be designed simply. Decoding preprocessing can separate the Frame Check Sequence（FCS） field from the Ethernet frame and restore the output data of the encoding preprocessor, which can simplify the CRC verifying circuit design. The traditional XOR circuit is optimized in the implementation of CRC encoding and verifying,which can reduce gate delay and improve computation speed. It can also switch the CRC encoding and verifying method automatically for compatibility with the existing Ethernet. Experimental results show that the proposed method not only occupies less logical resource, but also has faster computation speed and realizes real-time output compared with other three methods. Meanwhile 10 Gigabit Ethernet. , it also satisfies the 156. 25 MHz timing requirements for

关 键 词：循环冗余校验 10G以太网 并行 循环冗余校验魔数 门延时 逻辑资源 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]