基于Verilog的FIR数字滤波器设计与仿真  

Design and simulation of FIR digital filter based on Verilog

作　　者：何蕴良 耿淑琴[1] 汪金辉[1] 

机构地区：[1]北京工业大学电子信息与控制工程学院,北京100022

出　　处：《现代电子技术》2016年第10期1-4,共4页Modern Electronics Technique

基　　金：国家自然科学基金(61204040;60976028);教育部博士点基金(20121103120018);北京市教育委员会科技计划面上项目(JC002999201301);北京市自然科学基金资助(4152004)

摘　　要：设计一种基于Verilog的FIR数字低通滤波器。在结构上改变了以往乘法器和加法器的简单结合,利用分布式算法构造查找表进行乘累加运算,节约资源占用并且提高运算速率。利用Matlab工具设计和获取滤波器参数,并且进行仿真验证。滤波器参数量化后形成查找表,利用Verilog HDL语言对硬件电路模块进行设计描述,并且用Model Sim进行整个硬件电路系统的功能仿真,验证了设计的正确性。设计在速度和面积方面做了折中和优化,成功实现了数字滤波的功能。A FIR digital low-pass filter based on Verilog was designed and changed in its the structure. It isn＇t a commonly used simple combination of multipliers and adders,but the distributed algorithm was used to construct a lookup table to achieve the multiply-accumulate operation. Resource occupation was reduced and the operating rate was improved by this way. The Matlab was used to obtain parameters of the filter. The look-up table is formed by quantification of the parameters. The hardware circuit modules are designed and are described with Verilog HDL. The functional simulation of the whole hardware circuit system was conducted to verify correctness of the design by Model Sim. A compromise and optimization in speed and area were made,by which the functions of digital filtering were achieved successfully.

关 键 词：VERILOG 数字滤波器 分布式算法 FIR 

分 类 号：TN713.34[电子电信—电路与系统]