基于FPGA的处理器间高精度时钟同步通信机制  

FPGA-based communication mechanism with high-precision clock synchronization between processors

作　　者：蒋欣[1] 唐超 白晨[1] 

机构地区：[1]中航工业西安航空计算技术研究所,陕西西安710068 [2]驻六三一所军事代表室,陕西西安710068

出　　处：《现代电子技术》2016年第10期92-95,共4页Modern Electronics Technique

基　　金：航空基金项目(20121931002)

摘　　要：为了保证嵌入式设备运行的稳定性和可靠性,都会应用双余度的CPU来共同管理硬件资源,协调任务调度和处理CPU的高速外设接口数据,因此,该文介绍一种在具有高效数字时钟管理器的FPGA上产生高精度、高稳定度时钟同步信号,用来保证CPU间的精确同步通信,达到高效的公共资源管理、合理的任务调度以及相互比对的数据计算。In order to ensure the stability of embedded devices running and high reliability,are applied dual redundant CPU to co-management of hardware resources,task scheduling and coordination process CPU speed peripheral interface data,therefore,in this paper,a highly efficient digital generating clock management FPGA-precision,high-stability clock synchronization signal is used to ensure accurate synchronous communication between the CPU,in order to achieve efficient management of public resources,reasonable task scheduling and the mutual alignment of data calculation.

关 键 词：FPGA 同步通信 处理器 时钟信号 

分 类 号：TN710-34[电子电信—电路与系统]