高稳定性高瞬态响应无片外电容LDO的设计  

Design of Off-Chip Capacitor-Free Low-Dropout Linear Regulator with High-Stability and Fast-Transient-Response

作　　者：谢海情[1] 肖正[1] 唐俊龙[1] 周斌腾 曾承伟 陈希贤[1] 

机构地区：[1]长沙理工大学物理与电子科学学院,长沙410114

出　　处：《半导体技术》2016年第6期416-420,共5页Semiconductor Technology

基　　金：国家科技支撑计划资助项目(2014BAH28F04);国家自然科学基金资助项目(61404011);湖南自然科学基金资助项目(2015JJ3001);湖南省高校科技创新团队支持计划资助项目;长沙理工大学近地空间电磁环境监测与建模湖南省普通高校重点实验室开放基金资助项目

摘　　要：基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过冲状态下开启从LDO输出端到地的快速放电通路,欠冲电压改善电路通过电容耦合获得反映LDO输出电压瞬态变化的采样信号,经反向放大后加速功率管栅极电容放电,进而通过功率管对LDO输出电容充电。仿真结果表明,在TT工艺角下该低压差线性稳压器的空载相位裕度为64.57°,满载相位裕度为62.58°,过冲电压为40 m V,欠冲电压为97.6 m V,线性调整率为0.733‰;负载调整率19μV/m A;电源电压抑制比(PSRR)为-73 d B。An off-chip capacitor-free low dropout linear regulators （LDO） was designed with high stability and fast transient response based on Nuvoton 0.5 Ixm 5 V standard CMOS process. An overshoot voltage circuit and an undershoot voltage circuit module were designed to cut down overshoot voltage and undershoot voltage respectively, and without disturbing each other. The LDO output voltage and the re- ference voltage were compared by overshoot voltage improvement circuit. The fast discharge path from LDO output to ground was opened with undershoot voltage, the sampling signal of output voltage of LDO was acquired by capacitance coupling with undershoot voltage improvement circuit. The sampling signal was reverse amplified to discharge the gate capacitance of the power transistors rapidly. And then charging the output capacitor of LDO by power transistors. The simulation results show that under TT process corner, the no-load phase margin of the LDO is 64.57 -, and the full-load phase margin of the LDO is 62.58°. Overshoot voltage is 40 mV. Undershoot voltage is 97.6 mV. Linear adjustment rate is 0. 733 ‰, load regulationrate is 19 μV/mA and power supply rejection ratio （PSRR） is -73 dB.

关 键 词：稳定性 瞬态响应 低压差线性稳压器 无片外电容 瞬态增强电路 

分 类 号：TN432[电子电信—微电子学与固体电子学] TM44[电气工程—电器]