GRNN在FPGA中实现方法研究  

Study on the method of implementing GRNN on FPGA

作　　者：闫海亮[1] 崔桂雪 于毅[1] 董兵超[1] 李振新[1] 

机构地区：[1]新乡医学院生物医学工程学院,河南新乡453003

出　　处：《电子设计工程》2016年第11期170-172,176,共4页Electronic Design Engineering

基　　金：国家自然科学基金支持项目(61305147);河南省自然科学基金支持项目(122300410120;13A416858)

摘　　要：为了提高脑机接口(Brain-computer interface,BCI)中分类算法运行速度,以及减小BCI数字信号处理设备体积,将脑机接口中用于脑电信号分类的广义回归神经网络(General regression neural network,GRNN)算法经MATLAB仿真之后,在Quartus II 13.0中使用Verilog HDL编程实现基于二进制浮点数运算的GRNN算法,并下载到altera公司Cyclone V 5CEFA9 FPGA芯片中验证。当外部时钟使用100 MHZ时,在FPGA中GRNN的运行时间是76 us,并且分类结果与MATLAB完全相同。而MATLAB中运行一次GRNN算法的时间为90.885 ms。因此,该设计可以在减小脑机接口设备体积和提高分类算法运行速度的同时,还能保证结果的精确性。In order to increase the running speed of the classification algorithm and reduce the equipment volume in braincomputer interface（BCI）, GRNN used for brain electrical signal classification is implemented on FPGA by using the Verilog HDL programming in Quartus II 13.0 software after the simulation in MATLAB. GRNN＇s running time is 76 us on FPGA when the external clock is 100 MHZ, and The classification results is same with MATLAB. However, the elapsed time of GRNN in MATLAB is 90.885 ms. Therefore, this design can not only reduce equipment volume and improve the running speed of classification algorithm in BCI but also can ensure the accuracy of the results.

关 键 词：脑机接口 广义回归神经网络 FPGA 浮点数算法 

分 类 号：TN492[电子电信—微电子学与固体电子学]