低成本BIST映射电路的设计与优化  

The Low Cost BIST Mapping Logic Optimization for Digital Integrated Circuits Testing

作　　者：张玲[1] 王伟征[2] 

机构地区：[1]湖北理工学院计算机学院,湖北黄石435003 [2]长沙理工大学计算机与通信工程学院,长沙410004

出　　处：《微电子学》2016年第3期324-327,共4页Microelectronics

基　　金：国家自然科学基金资助项目(61303042;61472123);湖北省自然科学基金资助项目(2014CFC1091);湖北理工学院创新人才项目(13xjz05c);湖北理工学院优秀青年科技创新团队项目(13xtz10);湖北理工学院大学生创新项目(13cx25)

摘　　要：低成本BIST利用映射电路对自测试线形反馈移位寄存器进行优化,将对故障覆盖率无贡献的测试向量屏蔽掉,有效提高了故障覆盖率,降低了测试功耗。映射电路的设计是低成本BIST设计的关键,为了降低其硬件开销和功耗、提高参数性能,该映射逻辑电路对测试向量的种子进行映射,并通过相容逻辑变量合并、布尔代数化简等方法对映射电路进行优化,有效地降低了测试应用时间、测试功耗和硬件开销。To improve the fault coverage and reduce test cost, a low cost BIST was used to mask the test vectors that had no contribution to the fault coverage by the mapping logic unit. The performance of the mapping logic unit had a significant impact on the BIST. A new mapping logic unit design solution was proposed, which had made mapping to the determined test vector seeds, thus both the hardware cost and the test power had been reduced. Some simplified methods such as compatible variables merging and Boolean algebra simplifying, were used to reduce the hardware cost. The experimental results proved that the mapping logic unit could reduce test applied time and test power with low hardware cost.

关 键 词：内建自测试 映射电路 硬件开销 

分 类 号：TN306[电子电信—物理电子学]