一种基于时钟抽取偏置电压技术的存储器位线  

A Local Bit Line Based on Clock-Extracted Bias Voltage for Memory

作　　者：杨泽重 汪金辉[1] 侯立刚[1] 耿淑琴[1] 彭晓宏[1] 

机构地区：[1]北京工业大学集成电路与系统研究室,北京100124

出　　处：《微电子学》2016年第3期402-406,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61204040;60976028);教育部博士点基金资助项目(20121103120018);北京市教育委员会科技计划面上项目(JC002999201301);北京市自然科学基金资助项目(4152004)

摘　　要：基于一种新型时钟延时单元,设计了一种片上存储器的位线。在不增加版图面积的前提下,通过周期性地改变保持管的衬底偏置电压,减小了短路功耗、泄漏功耗和延迟时间,同时增加了电路的抗工艺波动能力。在SMIC 65nm工艺下,完成了传统位线、改进后的位线以及静态随机存取存储器(SRAM)的设计。仿真结果表明,在1GHz时钟频率下,改进后的两种位线与传统位线相比,功耗延迟积分别减小了19.1%和15.9%。最后,通过蒙特卡洛分析可知,改进后的位线相比于传统位线具有较强的抗工艺波动能力,即功耗延迟积的方差减小了97.1%。Based on a novel clock delay unit, a kind of bit lines of on-chip memories was designed. Without increasing the implementation hardware overhead, the body bias voltage of PMOS keeper was changed periodically to decrease the short circuit power consumption, leakage current, delay time, so to enhance the robustness to process variations. The conventional bit lines, the improved bit lines, and the SRAM were designed in SMIC 65 nm process. The simulation results showed that two kinds of the improved bit lines achieved 19.1% and 15.9% power- delay-product reduction respectively at 1 GHz clock frequency as compared to conventional bit lines. Moreover, through the Monte Carlo simulation, the proposed bit lines showed more robustness to process variations as compared to conventional ones. The variance of the power-delay-product was reduced by 97.1%.

关 键 词：存储器 位线 衬底偏置 抗工艺波动能力 

分 类 号：TN433[电子电信—微电子学与固体电子学]