CMOS半加器电路鲁棒性设计  

Circuit Robustness Design of CMOS Half-Adder

作　　者：刘春娟[1] 徐晓瑞[1] 杨超山 

机构地区：[1]兰州交通大学电子与信息工程学院,甘肃兰州730070

出　　处：《兰州交通大学学报》2016年第3期68-71,共4页Journal of Lanzhou Jiaotong University

基　　金：国家自然科学基金(61366006)

摘　　要：在数字电路设计中,电路逻辑功能和性能参数会随着数字逻辑器件的容差、延迟时间的改变而发生变化,甚至会引起不正常的逻辑关系.随着集成度不断提高,这种偏差严重影响电路的成品率,增加了电路设计的复杂性和成本.采用基于OrCAD/Pspice的最坏情况模拟及对器件模糊时间影响的抑制,对半加器逻辑电路参数进行适当修正,降低了输出结果不确定性及脉冲变窄或异常故障.所设计的加法器电路在满足原逻辑功能基础上,在指定的模糊时间变化范围内,电路稳定性得到明显提高,达到增强其鲁棒性的目的.In digital circuit design, circuit functions and performance parameters could be influencedby the tolerance and delay time of digital logic device, causing abnormal logic output, which willlead to the increase in the complexity and cost of the circuit design with the ever-increasing integration.The parameters of half-adder logic circuit are appropriately adjusted by the worst-case analysisand fuzzy time suppression based on OrCAD/Pspice. And the simulation results show thatthe output uncertainty and the pulse narrowing or abnormal fault are fully avoided. The circuitstability has been significantly improved besides the original logic functions within a specifiedfuzzy time, so that the robustness of the half-adder circuit is enhanced greatly.

关 键 词：半加器 鲁棒性 模糊时间 

分 类 号：TN432[电子电信—微电子学与固体电子学]