基于FPGA的数字分接器及同步复接器设计  

Design of Synchronous Multiplexer and Digital Demultiplexer Based on FPGA

作　　者：李奕聪 邵建龙[1] 

机构地区：[1]昆明理工大学信息工程与自动化学院,昆明650000

出　　处：《微处理机》2016年第3期93-96,共4页Microprocessors

摘　　要：随着通信系统对数据传输容量和传输速率的要求越来越高,数字复接和分接技术在数字通信系统中的地位越来越重要,复接器和分接器成为通信系统中的基本器件,基于FPGA对其进行了建模和设计。用FPGA设计的分接器和复接器最大的优势是使用灵活,可以作为IP核集成到其他模块中,分接器和复接器的参数可以灵活调整。复接器是基于时分复用原理,把几路低速码流合并成合路高速码流,分接器是将合路高速信号还原成低速支路信号。用4路信号对复接器和分接器进行了测试验证,并给出了内部各个模块详细的时序图。测试结果表明,整个系统结构简单,处理延时小、工作效率高。For data transmission capacity and transmission rate,the requirement for communication system becomes higher and higher,and digital multiplex and demultiplex play an important role in digital communication system. Demultiplexer and multiplexer,as basic devices in digital communication system,are designed and modeled based on FPGA in this paper. The most advantage of synchronous multiplexer and digital demultiplexer designed by FPGA is flexibility. They can be used as IP core to integrate into other models and their parameters can be modified conveniently. The multiplexer merges several low-speed streams into high- speed data stream,and the demultiplexer restores the high- speed signals to the lower speed branch ones. Multiplexer and demultiplexer are tested by four signals,and the internal timing diagrams of each module are given in detail. The result shows that entire system has advantages of simple structure,low delay and high efficiency.

关 键 词：FPGA芯片 同步复接器 分接器 帧同步 内码产生器 时序发生器 分路器 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]