一种基于FPGA的抗辐射加固星载ASIC设计方法  

A Design Method for Radiation Hardened Space-borne AISC Based on FPGA

作　　者：常克武 王海涛[2] 张弓[2] 汪路元[2] 

机构地区：[1]中国卫星导航系统管理办公室,北京100054 [2]北京空间飞行器总体设计部,北京100094

出　　处：《航天器工程》2016年第4期74-80,共7页Spacecraft Engineering

摘　　要：针对静态随机存储器(SRAM)型现场可编程门阵列(FPGA)空间应用的问题,提出了基于FPGA星载抗辐射加固专用集成电路(ASIC)设计的全流程,并重点对扫描链设计、存储器内建自测试、自动向量生成、ASIC封装设计、散热设计、加电振动试验等关键点的设计方法和注意事项进行了介绍。通过设计、测试、封装、试验,实现了基于静态随机存储器型FPGA转化为抗辐射加固ASIC。ASIC抗辐射总剂量大于100krad(Si),抗单粒子闩锁(SEL)阈值大于75 MeV·cm^2/mg,抗单粒子翻转(SEU)阈值大于22 MeV·cm^2/mg,满足空间应用的要求,具有很好的应用前景。Focusing on the problem of SRAM applied in space environment,this paper presents a design flow of a space-borne radiation hardened ASIC（application specific integrated circuit）whose design is based on FPGA,mainly introduces the design methods and related consideration of scan chain,MBIST（memory built in self test）,ATPG（automatic test pattern generation）,package design,heat dissipation and electrified vibration test which are key poits to the process of ASIC design.Through design,verification,package and test,the SRAM converts to radiation hardened ASIC.The total anti-radiation dose of this ASIC is greater than 100krad（Si）.Moreover,the single event latch-up threshold energy of this AISC is greater than 75MeV·cm-2/mg,while its SEU threshold energy is greater than 22MeV·cm-2/mg.Anti-radiation characteristics of ASIC will gives it a bright future for extension.

关 键 词：专用集成电路 空间环境辐射 单粒子效应 设计流程 

分 类 号：V446[航空宇航科学与技术—飞行器设计]