集成电路边界扫描测试中的电路网表结构分析  

Circuit Netlist Structure Analysis for Integrated Circuits Boundary Scan Testing

作　　者：陈翎[1] 潘中良[1] 

机构地区：[1]华南师范大学物理与电信工程学院,广东广州510006

出　　处：《数字技术与应用》2016年第7期70-73,共4页Digital Technology & Application

基　　金：广东省自然科学基金(2014A030313441);广东省科技计划项目(2013B090600063;2014B090901005);广州市科技计划项目(201510010169)资助

摘　　要：边界扫描测试能够对电路芯片间的互连和每个芯片内部的逻辑功能等进行检测,可以检测出电路中多种类型的故障,以确保电路具有较高的可靠性和电路功能的正确性。本文首先说明了边界扫描测试的结构;其次,给出了边界扫描测试软件的设计方法,对它的如下的主要模块即电路描述的输入、电路网表结构分析、完备性测试、互连测试、芯片内部功能的测试、测试结果输出等的功能进行了说明,重点对电路网表结构分析这个模块的实现进行了详细阐述。The boundary scan testing can detect the interconnections among chips and the logic functions of each chip, it is able to detect the faults in the circuits, and can ensure the high reliability and the correctness of circuit functions. First of all, the structure of boundary scan testing is demonstrated in this paper. Secondly, the design method of boundary scan testing software is given, the functions of its main modules are shown, the modules include the circuit description input, circuit netlist structure analysis, interconnection testing, chip internal logic testing and test results output, etc. The implementation of circuit net.list structure analysis is described in detail.

关 键 词：集成电路 边界扫描 测试方法 软件程序 网表结构分析 

分 类 号：TN407[电子电信—微电子学与固体电子学]