基于IODELAY原语SAR载荷模拟器延迟单元设计  

Design of Delay Unit in SAR Load Simulator Based on IODELAY Primitive

作　　者：赵君[1] 艾铁柱[1] 张宇坤[1] 

机构地区：[1]中航工业西安航空计算技术研究所,西安710065

出　　处：《计算机测量与控制》2016年第8期240-243,共4页Computer Measurement &Control

基　　金：航空科学基金-青年基金(2014ZD31006)

摘　　要：针对星载合成孔径雷达中数传分系统测试时，需要进行接收数据时序拉偏测试需求，提出一种基于FPGA原语的SAR载荷模拟器延时单元设计方法，该延迟单元采用IODEIAY原语，通过时序约束实现正反向时钟与数据时序拉偏功能，同时分析了FPGA内部逻辑资源约束对时序拉偏功能的影响；仿真与试验结果表明，基于该延迟单元的SAR载荷模拟器时钟与数据时序调整范围可达-6-6ns，步进1ns，系统运行稳定，满足设计要求。In allusion to the requirement of timing perturbation between data and clock, which is in process of testing data transmission subsystem of spaceborne synthetic aperture radar （SAR）, a new design of SAR load simulator, which is based on delay unit with FPGA primitive, is proposed in this thesis. For testing data transmission subsystem, the delay unit, completing timing perturbation between data and clock, consists of IODELAY primitive by timing rules. And it also analyzes the influence of the logic resource constraint in FPGA on the timing perturbation function. Finally, the performance and robustness are assessed through the simulation and test, whose result shows that the range of timing perturbation is from -6ns to 6ns with 1ns step. The system runs stably and meets the design requirements.

关 键 词：星载合成孔径雷达 数传分系统 载荷模拟器 IODELAY原语 

分 类 号：TP957.51[自动化与计算机技术]