嵌入式存储模块低功耗设计技术  

Low Power Design Technology of Embedded Memory

作　　者：何晓宇[1] 

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110032

出　　处：《微处理机》2016年第4期23-26,共4页Microprocessors

摘　　要：随着集成电路进入深亚微米和纳米级工艺阶段,集成电路尤其是片上系统(SOC)的功耗问题已经成为制约新一代电子系统发展最主要的因素之一。片上系统中最为重要的除了处理器单元就是与之配套的嵌入式存储器,其功耗占到了整个片上系统功耗的百分之六十以上。因此,嵌入式存储器的低功耗设计对提高整个片上系统性能和降低系统功耗至关重要。针对几种常用的嵌入式存储器模块介绍了低功耗设计技术并进行了讨论,经过我所自行研制的SOC验证,低功耗效果明显。Integrated circuit, especially system on chip （ SOC ） power consumption, becomes more and more important in the technology of deep sub - micron and nanometer. In SOC, the processor and the embedded memory are important modules. The Embedded memory power consumption accounts for 60% of whole SOC. Thereby, the design of the embedded memory low - power is the key point to improve SOC performance and reduce system power consumption. The thesis studies low - power design technology in the embedded memory and the method has been proved by manufactured SOC chip.

关 键 词：数字系统 嵌入式存储器 片上系统 缓冲器(Cache) 寄存器堆 低功耗设计 

分 类 号：TN47[电子电信—微电子学与固体电子学]