基于FPGA的芯片引脚边缘检测系统的设计与实现  

Design and implementation of edging inspection system of chip pins based on FPGA

作　　者：邓海涛[1] 李建辉[2] 吴捷[1] 方逸裕 焉胜虎 陈耀文[1] 

机构地区：[1]汕头大学工学院,汕头515063 [2]汕头华汕电子器件有限公司,汕头515031

出　　处：《中国体视学与图像分析》2016年第2期163-172,共10页Chinese Journal of Stereology and Image Analysis

基　　金：汕头市科技计划项目(A201400150);汕头大学学术创新团队项目(ITC12002)

摘　　要：目的为了提高芯片封装外观质量检测速度并降低检测成本,基于FPGA开发芯片引脚边缘检测系统。方法根据FPGA并行处理高效率的特点,搭建FPGA+SDRAM高性能硬件处理平台,利用Quartus II软件采用Verilog HDL硬件描述语言编写程序实现对芯片引脚进行边缘检测。结果该平台仅使用FPGA少量的逻辑资源实现对芯片引脚进行有效的边缘检测。结论该检测系统提高了工业应用中芯片引脚边缘检测的效率,同时可应用于ARM、DSP芯片封装外观质量检测。Objective To speed up the quality inspection of chip packaging in appearance and reduce its cost, we developed an edge detection system based on FPGA chip pins. Methods According tocharacteristics of the parallel processing and high efficiency of FPGA, edge detection of chip pins was accomplished on a high speed FPGA ＋ SDRAM hardware process platform coded with Verilog HDL hard- ware description language using Quartus II software. Results This platform can efficiently detect chip pins edges by using only a small amount of logical resource on FPGA. Conclusions The detection system can improve the efficiency of chip pins detection in industrial production, and further meet the demand in ARM and DSP for chip packaging appearance quality inspection .

关 键 词：现场可编程门阵列技术 集成电路 边缘检测 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]