基于串行RapidIO的Buffer层设计  

A Buffer Layer Design in Serial RapidIO

作　　者：任雪倩 李金城[2] 赵建中[1] 张锋[1] 

机构地区：[1]中国科学院微电子研究所智能感知研发中心,北京100029 [2]北京交通大学电子信息工程学院,北京100044

出　　处：《微电子学与计算机》2016年第9期47-50,共4页Microelectronics & Computer

基　　金：国家科技重大专项(2014ZX02302002)

摘　　要：RapidIO是一种新兴的高性能互联总线,主要应用于嵌入式系统.作为串行RapidIO结构的重要组成部分,Buffer层负责保证数据包的可靠传输,并且在链路级流量控制中起着重要作用.对此提出了一种改进的buffer层结构,同时支持发送端流量控制和接收端流量控制两种模式.仿真结果表明,该buffer层有效地提高了buffer的空间利用率和传输效率.该设计在高性能嵌入式系统中具有一定的工程应用价值.RapidIO is an emerging high-performance interconnect technology for embedded system interconnection. As a very significant part of serial RapidIO, buffer layer helps to guarantee reliable packet delivery and plays an important role in link level flow control. In this paper, the design of an improved buffer layer in serial RapidIO endpoint is described in detail. Both transmitter-controlled flow control and receiver-controlled flow control are supported in this design. Simulation results show that the proposed buffer layer has better space utilization and higher transmission efficiency, compared with the referenced designs. It is valuable for high performance embedded system applications to some extent.

关 键 词：BUFFER RAPIDIO 流量控制 

分 类 号：TN4[电子电信—微电子学与固体电子学]