一种基于bang-bang鉴频鉴相器的全数字锁相环设计  

An All-digital Phase Lock Loop Based on Bang-bang PFD

作　　者：陈原聪 赵野[1] 王彤[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2016年第9期106-109,共4页Microelectronics & Computer

基　　金：中科院青年创新促进会基金(Y3YQ01R001)

摘　　要：提出一种基于bang-bang鉴频鉴相器和二进制搜索的全数字锁相环,该全数字锁相环主要由bang-bang鉴频鉴相器、带二进制搜索和自动增益调控的数字滤波器、基于阶梯型环形振荡器的三级数控振荡器组成,采用0.18CMOS工艺设计,仿真表明,该全数字锁相环频率输出范围为80~220 MHz,能够在80个周期内完成频率锁定,在500个周期内实现相位锁定,锁定时峰峰抖动22.55ps,RMS抖动3.342ps,整体功耗2.03mW@125 MHz左右.A king of all-digital phase lock loop based on bang-bang PFD is proposed in this paper. The ADPLL based on bang-bang PFD is eomposed of bang-bang PFD, digital filter with binary search and automatic gain controlled, and ladder-shaped ring digital controlled oscillator with three level control word. Simulation and verification are done about the DCO based on 0. 18μm CMOS process. The results show that the ADPLL output frequency range from 80 MHz to 220 MHz, finish the frequency locked in 80 cycles, phase locked in 500 cycles, the measured peak to peak jitter is about 22.55 ps, RMS jitter is 3. 342 ps. The ADPLL consumed a power of 2.03roW@ 125 MHz.

关 键 词：bang-bang鉴频鉴相器 二进制搜索算法 数字锁相环 

分 类 号：TN402[电子电信—微电子学与固体电子学]