基于矩阵三角化分解的Cholesky分解及FPGA并行结构设计  

Cholesky decomposition and parallel structure design based on matrix triangularization decomposition

作　　者：刘书勇[1] 林俊宇[1] 吴艳霞[1] 张博为[1] 

机构地区：[1]哈尔滨工程大学计算机科学与技术学院,哈尔滨150001

出　　处：《清华大学学报（自然科学版）》2016年第9期963-968,共6页Journal of Tsinghua University(Science and Technology)

基　　金：国家自然科学基金面上项目(61003036);计算机体系结构国家重点实验室开放课题(CARCH201301);中央高校基本科研业务经费专项基金(HEUCF100606)

摘　　要：矩阵运算是高性能计算中核心问题之一,矩阵分解是提高矩阵运算并行性的重要途径,飞速发展的FPGA为并行运算结构提供了有力的环境支持。该文基于子矩阵更新同一化算法实现了Cholesky分解,基于FPGA设计了相应的并行结构。实验结果表明:与通用处理器的软件实现相比,本文实现的Cholesky分解的FPGA并行结果在核心计算性能上可以取得10倍以上的加速比,该算法针对矩阵三角化计算过程具有更高的数据和流水并行性。Matrix computing is one of the core problems in high performance computing with matrix decomposition being an important way to improve the parallelism of matrix computations. FPGA gives a powerful environment for parallel computing. This study uses Cholesky decomposition based on a hardware-adaptive parallel sub-matrix identity updating algorithm. Its parallel structure is based on FPGA. Tests show that this structure achieves more than 10 fold speedup compared to general-purpose processors in terms of the kernel computational speed because the algorithm has better data-parallelism and pipeline-parallelism during matrix triangularization.

关 键 词：矩阵三角化分解 CHOLESKY分解 并行结构 现场可编程门阵列 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]