千兆以太网通信端口FPGA设计与实现  

Design and implementation of gigabit Ethernet communication port based on FPGA

作　　者：朱保琨 刘广文[1] 

机构地区：[1]长春理工大学电子信息工程学院,吉林长春130022

出　　处：《计算机工程与设计》2016年第9期2292-2298,共7页Computer Engineering and Design

摘　　要：为解决FPGA千兆以太网硬核媒体访问控制器建置与移植弹性低、整合难度大、特定结构下功能综合化造成资源消耗增加等问题,并达到控制器灵活性高、移植性强、黑箱式核心透明化的目的,提出一种千兆以太网解决方案。在Xilinx FPGA的IP LogiCORE物理接口收发器的基础上,通过逻辑设计实现MAC控制器,融入抓包功能,保证新型千兆以太网通信端口问题定位准确、高效、可控性好、透明度高、资源用量小、适应性强。通过实例对该方案进行仿真分析,分析结果验证了逻辑MAC控制器的可行性和有效性。The Gigabit Ethernet media access controller with FPGA implementation and transplantation of low elastic,the integration is difficult,under the specific structure function synthesis lead to resources consumtion increase and other issues,to reached controller has high flexibility,portability,box core transparent purpose.This paper puts forward the solution of a new Gigabit Ethernet,based on the Xilinx FPGA IP logicore physical interface transceiver,through logical design to achieve the MAC controller,and add the capture function,to ensure the new Gigabit Ethernet communication port positioning accuracy,efficiency,good controllability,high transparency,a small amount of resources,strong adaptability.In the paper,the simulation analysis of the proposed scheme is carried out to verify the feasibility and effectiveness of the MAC controller by examples.

关 键 词：千兆以太网 XILINX FPGA 逻辑MAC控制器 抓包 串行吉比特媒体独立接口 

分 类 号：TP393.11[自动化与计算机技术—计算机应用技术]