条件推测性十进制加法器的优化设计  

Design of Optimized Conditional Speculative Decimal Adders

作　　者：崔晓平[1] 王书敏[1] 刘伟强[1] 董文雯[1] 

机构地区：[1]南京航空航天大学电子信息工程学院,南京210016

出　　处：《电子与信息学报》2016年第10期2689-2694,共6页Journal of Electronics & Information Technology

摘　　要：随着商业计算和金融分析等高精度计算应用领域的高速发展,提供硬件支持十进制算术运算变得越来越重要,新的IEEE 754-2008浮点运算标准也添加了十进制算术运算规范。该文采用目前最佳的条件推测性算法设计十进制加法电路,给出了基于并行前缀/进位选择结构的条件推测性十进制加法器的设计过程,并通过并行前缀单元对十进制进位选择加法器进行优化设计。采用Verilog HDL对32 bit,64 bit和128 bit十进制加法器进行描述并在Model Sim平台上进行了仿真验证,在Nangate Open Cell 45nm标准工艺库下,通过Synopsys公司综合工具Design Compiler进行了综合。与现有的条件推测性十进制加法器相比较,综合结果显示该文所提出的十进制加法器可以提升12.3%的速度性能。There are increasing interests in hardware support for decimal arithmetic due to the demand of high accuracy computation in commercial computing, financial analysis, and other applications. New specifications for decimal floating-point arithmetic have been added to the revised IEEE 754-2008 standard. In this paper, the algorithm and architecture of decimal addition is studied comprehensively. A decimal adder is designed by using the parallel-prefix/carry-select architecture. The parallel-prefix unit is used to optimize the decimal carry select adder. The decimal adder has been realized by Verilog HDL and simulated with ModelSim. The synthesis results of this design by Design Compiler is also given and analyzed under Nangate Open Cell 45nm library. The results show that the delay performance of the proposed circuit can be improved by up to 12.3%.

关 键 词：十进制加法 条件推测十进制加法 并行前缀 进位选择加法器 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]