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作 者:王博[1] 杨建国[1] 林殷茵[1] Wang Bo Yang Jianguo Lin Yinyin(State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China)
机构地区:[1]复旦大学专用集成电路与系统国家重点实验室,上海201203
出 处:《半导体技术》2016年第10期769-773,788,共6页Semiconductor Technology
基 金:国家高技术研究发展计划(863计划)资助项目(2014AA032902)
摘 要:通过测试不同工艺条件下的导电丝形成算法与低阻阻值分布、烘烤失效率等的关系,研究了阻变存储器(RRAM)单元导电细丝形成过程对可靠性的影响,进一步对导电细丝形成过程的模型进行了优化。实验表明,随着脉宽的增大,操作电压幅值降低、成功率提高、烘烤失效率降低,进一步增加脉宽,烘烤失效率大大增加。通过比较不同工艺,发现在烘烤失效率降低时的脉宽条件(1 ms)下,氧化时间短、氧化功率大并且无退火条件的失效率高;而在烘烤失效率增加时的脉宽条件(10 ms)下,氧化时间短、氧化功率大并且无退火条件的失效率低。研究结果为设计RRAM单元操作算法提供了优化方向,同时通过对不同条件下RRAM单元可靠性的比较,优化了工艺配方。By testing the relationship between forming algorithm of the conductive filament,the resistance distribution of low resistance state and baking failure rate under different process conditions,the influence of conductive filament growth process of the RRAM cell on its reliability was studied and the conductive filament growth model was optimized further. The test results show that with the increasing of pulse width,the amplitude of set voltage is reduced,the set success rate is increased and the bake failure rate is decreased. However, further increasing the pulse width, the bake failure rate is increased. By comparing different processes,it shows that in the condition of pulse width( 1 ms) which leads to baking failure rate decreasing,the failure rate is highest under the process condition of shorter oxidation time,larger oxidation power and non-annealing. In the condition of pulse width( 10 ms)which leads to baking failure rate increasing,the failure rate is lowest under the process condition of shorter oxidation time,larger oxidation power and non-annealing. The results give a optimum modification to design the operation algorithm for the RRAM cell. At the same time,the process recipe were optimized by comparing the reliabilities of the RRAM cell at different conditions.
关 键 词:氧化铝/氧化钨 阻变存储器(RRAM) 形成算法 可靠性 阻变机制 工艺优化
分 类 号:TN304.21[电子电信—物理电子学] TP333.8[自动化与计算机技术—计算机系统结构]
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