SHA-1算法的高速ASIC实现  

The High-Throughput ASIC Implementation of SHA-1 Algorithm

作　　者：杜晓婧[1,2] 李树国[1,2] 

机构地区：[1]清华大学微电子学研究所,北京100084 [2]清华信息科学与技术国家实验室,北京100084

出　　处：《微电子学与计算机》2016年第10期19-23,27,共6页Microelectronics & Computer

摘　　要：SHA-1算法是一种国际标准的安全杂凑算法.为提高SHA-1算法的吞吐率,提出了一种新的五合一架构,该架构使SHA-1算法的迭代压缩由原来的80轮变为16轮,并可使每轮中某些f函数和部分加法移到关键路径外,从而缩短了关键路径,提高了吞吐率.在SMIC 65nm的工艺下,吞吐率达到12.68Gb/s,高于已发表的同类设计.SHA-1 algorithm is one of the national standard for Secure Hash Algorithm. For the sake of accelerating the throughput of SHA-1 algorithm, a new 5-in-1 structure is proposed in this paper. This structure reduces the compression function from original 80 rounds to 16 5-in-1 rounds and in each round some functions f and adders can be moved out of the critical path. Based on this, we can shorten the critical path and increase the throughput. In SMIC 65nm technology, the throughput of SHA-1 can achieve 12. 68 Gb/s, which is higher than that of other reported designs and can meet the requirement of high throughput. This design also supports resuming transfer.

关 键 词：SHA-1算法 高吞吐率 ASIC实现 逻辑化简 

分 类 号：TN49[电子电信—微电子学与固体电子学]