千万门级FPGA装箱实现及验证  

Packing Implementation and Verification for 10M-gate FPGA

作　　者：胡凯[1] 董志丹 惠锋 李卿 董宜平 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214072 [2]无锡中微亿芯有限公司,江苏无锡214072

出　　处：《电子与封装》2016年第10期32-35,42,共5页Electronics & Packaging

摘　　要：装箱是FPGA工具设计流程中关键的一步,是综合、工艺映射和布局的桥梁,在很大程度上影响了电路的速度和功耗。基于千万门级FPGA xc5vlx20tff323-2器件,对XST综合工具综合后的网表进行装箱,并把装箱结果转换为XDL格式文件,使用Xilinx工具验证其正确性。Packing is a key step in the FPGA tool flow that straddles the boundaries between synthesis,technology mapping and placement, and that greatly influences circuit speed, density, and power consumption.In the paper, xc5vlx20tff323-2 device, a 10M-gate FPGA, is described in detail covering the packing of the net list synthesized by XST tool, conversion to XDL file and verification by Xilinx tools.

关 键 词：FPGA 装箱 验证 

分 类 号：TN402[电子电信—微电子学与固体电子学]