基于CPLD的面阵CCD驱动  

Driving the Area Array CCD Based on CPLD

作　　者：赵锡年 瑚琦[1] 高鹏飞[1] 

机构地区：[1]上海理工大学光电信息与计算机工程学院,上海200093

出　　处：《电子科技》2016年第11期35-37,40,共4页Electronic Science and Technology

摘　　要：为实现对面阵CCD的驱动,采集实时图像,设计了电源驱动和数据转换系统。系统采用复杂可编程逻辑器件(CPLD)对一款薄型背照式面阵CCD进行驱动。使用Verilog硬件描述语言(HDL)编写CPLD控制模块,控制CCD的信号采集、信号转移和信号传输。根据CCD的数据手册,设计CCD所需的电源,以便对其进行驱动。利用A/D芯片中的相关双采样(CDS)特点,对输出的视频信号进行处理,过滤视频信号中的复位噪声和1/f等低频噪声,提高系统的信噪比。该系统采用CPLD作为核心控制器件,充分利用了CPLD高速并行且"可编程"的特点,和CCD对环境变化的高度敏感,使得信号采集和传输的速率均较快,且输出视频信号稳定。In order to implement the driven of area array CCD and collect real-time image,we have designed a power driven and data conversion system. Based on the extensive use of CCD, this system drives a back-thinned area array CCD by the complex programmable logic device（CPLD）. The CPLD control module is written in Verilog hardware description language （HDL）, which is used to control the CCD＇s signal acquisition, signal transfer and signal transmission. According to the CCD data sheet, designing some power which the CCD needs to drive the CCD. Handling the output video signal and removing the low frequency noise such as reset noise and 1/f in filtered video signal and improving the SNR of system by the characteristics of the correlated double sample （CDS） of A/D chip. The system uses the CPLD as the core control device and makes full use the characteristics of CPLD, such as the high-speed parallel , ＂programmable＂ and the highly sensitive to the environment changing to make the speed of the signal acquisition and transmission speed be fast, and to make the output video signal be stable.

关 键 词：薄型背照式面阵CCD 复杂可编程逻辑器件 VERILOG HDL 

分 类 号：TN386.5[电子电信—物理电子学]