应用于超宽带收发机的多相时钟生成器的设计  

A Multiphase Clock Generation for UWB Transceiver

作　　者：刘小峰[1] 刘铛 李宇根[1] 王志华[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《微电子学与计算机》2016年第11期87-90,94,共5页Microelectronics & Computer

摘　　要：设计了一款用于超宽带(UWB)收发机的多相位基带时钟生成器.该时钟生成器通过分析锁相环(PLL)和延时锁定环(DLL)结构的共性,提出了一种全匹配的压控振荡器/压控延时线(VCO/VCDL)双模可配置结构,使时钟生成器可以分别在PLL/DLL两种模式下工作,为UWB收发机提供2GHz 10相位的基带时钟信号.该电路基于TSMC 65nm CMOS工艺设计实现,有效面积为0.03mm2.根据测试结果,PLL模式工作时输出相位噪声为-85.04dBc/Hz@1 MHz,参考杂散功率为-46.89dBc.供电电压为1V时,电路总功耗约为2.1mW.A multiphase baseband clock generation for UWB transceiver is presented. By combining the similarity of PLL and DLL＇s structure, a reconfigurable fully-matched VCO/VCDL with dual mode is proposed. The clock generation system with the proposed VCO/VCDL can work in PLL/DLL mode separately, and provide 10 phase baseband clock signals which is 2 GHz The chip is fabricated in TSMC 65 nm CMOS process, and the active area is only 0. 03 mm2. The testing results show that the output phase noise is -85. 04 dBc/Hz@l MHz and the reference spur is -46. 89 dBc in PLL mode. The power consumption of the clock generation is about 2. 1 mW under the 1 V supply.

关 键 词：超宽带收发机 多相时钟生成 锁相环 延时锁定环 双模可配置 

分 类 号：TN402[电子电信—微电子学与固体电子学]