基于FPGA的宽带ADC采集系统的设计与实现  

Design and implementation of a wideband ADC acquisition system based on FPGA

作　　者：李赛辉[1] 刘剑[1] 蒋廼倜 李伟[1] 

机构地区：[1]中国船舶重工集团公司第七二四研究所,南京211153

出　　处：《雷达与对抗》2016年第4期41-44,共4页Radar & ECM

摘　　要：针对宽带采集系统设计中的时钟抖动、高速ADC电路、高速数据缓存和高速数据传输等问题,阐述了一种基于FPGA为主控芯片、DDRII作为缓存模块、采样速率为500 MHz的宽带ADC数据采集系统的设计与实现。分析了各部分对采集系统的影响和在设计中需要注意的问题。对设计的系统进行了性能测试。In view of the problems such as the clock jitter,high-speed ADC circuit,high-speed data buffer and data transmission in the design of the wideband acquisition system,a wideband ADC data acquisition system is designed and implemented,with the FPGA as the main control chip,the DDRII as the buffer module,and the sampling rate of 500 MHz. The effect of each part on the acquisition system and the significant problems in the design are analyzed,and the performance of the system designed is tested.

关 键 词：雷达 信号处理 FPGA 采集系统 ADC 

分 类 号：TN911.7[电子电信—通信与信息系统]