大容量同步双端口SRAM的仿真方法  

Research on Simulation Method of Large Capacity Synchronous Dual-port SRAM

作　　者：周云波[1] 李晓容[1] ZHOU Yunbo LI Xiaorong(China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214072, China)

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214072

出　　处：《电子与封装》2016年第12期35-39,共5页Electronics & Packaging

摘　　要：根据大容量同步双端口SRAM(静态随机存储器)功能多、时序严格、存储单元数目巨大的特点,提出了一套用于功能复杂的大容量SRAM仿真验证的激励生成和后仿真验证方法。该方法不仅克服了Hsim仿真激励文件编写耗时、不易修改的缺点,而且解决了大容量双端口SRAM后仿真速度缓慢、占用大量硬件资源的问题,在很大程度上缩短了设计周期,保证了投片成功。芯片采用中芯国际0.13μm CMOS工艺流片,实测结果验证了该仿真方法是准确有效的。The large capacity synchronous dual-port SRAM is usually of multi-function, critical time sequence and huge number of storage units. The paper proposes the method of simulation sources generation and parameter extraction for SRAM. The method not only overcomes the shortcomings of the conventional＇HSIM＇ tool but also increases the speed and saves hardware resources during post-layout simulation of large capacity dual-port SRAM. It greatly shortens the design cycle. The chip is manufactured by SMIC 0.13 μm CMOS process. The experiment results verify the accuracy and effectiveness of the simulation method.

关 键 词：双端口同步SRAM 激励文件 层次化 关键路径 

分 类 号：TN402[电子电信—微电子学与固体电子学]