可测性设计测试向量低功耗设计方法  

Low power design of testability test vector design method

作　　者：胡海涛[1] 钟明琛[1] 陈大为[1] 陈莉 

机构地区：[1]中国电子技术标准化研究院集成电路测试与评价工业和信息化部重点实验室,北京100176 [2]北京青鸟元芯微系统科技有限责任公司,北京100871

出　　处：《电子测量技术》2016年第11期46-50,共5页Electronic Measurement Technology

基　　金：国家重大专项(2012ZX01022-002-002)资助项目

摘　　要：随着半导体工艺尺寸的不断缩小和芯片集成度的提高,大规模、高性能处理器中的测试面临着许多严峻的挑战,其中,测试功耗已经成为大规模、高性能处理器生产测试中的关键性问题。可测性设计中的功耗较常规功能模式下的的功耗更高,过高的测试功耗高会导致芯片结构损坏、可靠性下降、成品率降低和测试成本增加等问题。可测性设计技术是降低测试成本,提高测试质量的有效手段,但是在对电路进行可测性设计的过程中有可能会造成功耗问题更加严重。本研究对可测性设计的低功耗测试向量的X-Fill、时钟门控、功率分割等低功耗技术进行了介绍和分析,通过开源处理器LEON3作为实例,进行了实用的低功耗测试技术的分析和实验,提出可测性设计低功耗测试向量的设计方法。With the shrinking of the semiconductor craft size and the integration of IC chips ,the test of large‐scale , high‐performance processor is seriously challenged .The power consumed in testing has become a problem in large‐scale ,high‐performance processor production test .The power consumption of the circuit in DFT test mode is higher than that in the functional mode ,and it may lead to the problems such as chip structure damage ,decrease of the reliability ,decrease of the product rate and increase of the test cost .DFT is an effective means to reduce test cost and improve test quality ,but it is likely to cause more problems in the process of design for testability of circuit .This paper introduces the importance of low power DFT test vector such as X‐Fill ,clock gating ,retains the state of low power technology for the large‐scale , high‐performance processor , introduces and analyzes the practical low power consumption test technology with an example of open source processor LEON 3 ,finally summarizes the design method of testability design of low power consumption test vector .

关 键 词：可测性设计 低功耗 X-Fill 时钟门控 

分 类 号：TN407[电子电信—微电子学与固体电子学]