基于动态电路的高速发送端设计  

Design of a high-speed transmitter based on dynamic circuits

作　　者：孟时光 Meng Shiguang(State Key Laboratory of Computer Architecture（ Institute of Computing Technology, Chinese Academy of Sciences）, Beijing 100190 Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190 University of Chinese Academy of Sciences, Beijing 100049 Loongson Technology Corporation Limited, Beijing 100095)

机构地区：[1]计算机体系结构国家重点实验室(中国科学院计算技术研究所),北京100190 [2]中国科学院计算技术研究所,北京100190 [3]中国科学院大学,北京100049 [4]龙芯中科技术有限公司,北京100095

出　　处：《高技术通讯》2016年第7期625-630,共6页Chinese High Technology Letters

基　　金：国家"核高基"科技重大专项课题(2014ZX01020201;2014ZX01030101);国家自然科学基金(61521092;61432016)资助项目

摘　　要：为了降低高速串行接口中发送端的延迟,在研究、分析现有发送端结构的基础上,提出了新的数据跨时钟域传输方法并在实际电路中得到实现。此方法可以大幅降低数据跨时钟域传输时用于异步FIFO的延迟。而且,使用动态电路对高速发送端并串转换电路进行了晶体管级的改进,放松了关键路径的时序要求,使发送端整体电路能运行在更高的频率下。发送端电路使用40nm CMOS工艺实现,实际芯片测试数据表明,使用该电路的发送端可以稳定工作在13Gb/s的速率下。To lower the transmitter＇ s delay of a h domain crossing was presented and realized igh in -speed serial interface, a new data transmission method under clock practical circuit design based on investigating and analyzing existing transmitter structures. This method can greatly reduce the delay for asynchronous FIFO during the data transmission under clock domain crossing. Moreover, the high-speed transmitter＇ s serializing circuits were improved at transistor level by using dynamic circuits to relax critical paths＇ timing requirement, so the transmitter＇ s whole circuit can work under the higher frequency. The proposed transmitter＇ s circuit was manufactured with the 40nm CMOS technology, and the testing results demonstrate that the transmitter using the circuit can stably work at the rate of 13Gb/s.

关 键 词：高速发送端 异步FIFO 并串转换 动态电路 跨时钟域 

分 类 号：TN402[电子电信—微电子学与固体电子学]