基于异步串行链接的FPGA布线算法  

An FPGA Routing Algorithm Based on Asynchronous Serial Links

作　　者：商信华[1] 

机构地区：[1]信阳农林学院信息工程学院,河南信阳464000

出　　处：《控制工程》2017年第1期33-39,共7页Control Engineering of China

基　　金：河南省科学技术研究重点项目(15A520095)

摘　　要：针对现场可编程门阵列(FPGA)的布线拥挤问题,为了提高布通率,提出了基于异步串行链接的FPGA布线框架,该框架由异步串行收发器和相应的快速布线算法组成,最大优势是将串行线路的合理框架成功应用于FPGA。首先,在FPGA中添加异步串行收发器;然后,运用post-routing算法更新FPGA布线,选择非关键且足够长的导线段附近的最优组,对其进行串行化。最后,异步串行数据传输后,将信号反串行化成并行信号。实验结果显示,在面积和功耗的代价合理的情况下,利用异步数据串行化能有效减少布线数量和布线拥挤(分别为18.81%和48.73%),同时系统性能并未有任何下降。该算法可用于开发集成度更高、更复杂的FPGA。For the issue of the routing congestion of field programmable gate array （FPGA）, a new FPGAframework is proposed to improve the routability, which consists of asynchronous serial transceivers and thecorresponding fast routing algorithm. The biggest advantage of this framework is the successful application ofthe reasonable framework of serial lines to FPGA. Firstly, some asynchronous serial transceivers are added inFPGA; Then, FPGA routing is updated by the post-routing algorithm, and the optimum around the non-criticalbut long wire segment is selected and serialized. After the asynchronous serial data transmission, the signals areanti-paralleled into serial signals. Experimental results show that in a case of reasonable cost consume andcertain area, the use of asynchronous serial data can effectively reduce the number of wires and routingcongestion （respectively 18.81% and 48.73%）, and the system does not have any performance decrease. Thisalgorithm can be used to develop more integrated and more complex FPGA.

关 键 词：可编程门阵列(FPGA) 异步串行收发器 布线拥挤 串行化 布通率 

分 类 号：TP47[自动化与计算机技术]