基于SOI-0.18 μm高PAE CMOS Class-E功率放大器  

A High PAE Class-E Power Amplifier Based on SOI-0.18 μm Process

作　　者：郑岩[1,2,3] 李志强[1,2] 刘昱[1,2] 黄水龙[1,2] 张海英[1,2] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]新一代通信射频芯片技术北京市重点实验室,北京100029 [3]中国科学院大学,北京100049

出　　处：《微电子学与计算机》2017年第2期63-67,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(61404166)

摘　　要：基于IBM SOI-0.18μm CMOS工艺,实现了高PAE的Class-E功率放大器.此放大器由两级构成.在输出级采用了负电容技术,抵消寄生电容,提高效率.输出级的共栅管采用自偏置,防止晶体管被击穿.驱动级采用Class-E结构,使得输出级能更好地实现开与关.两级之间使用了改善输出级电压和电流交叠的网络.通过使用这些技术,在2.8V电源电压下,功率放大器工作在2.4GHz的时候,输出功率为23.44dBm,PAE为58.99%.Based on IBM SOI-0. 18 μm CMOS process, a high PAE Class-E power amplifier is proposed. This power amplifier is composed of two stages. A negative capacitance is used at output stage in order to offset parasitic capacitance and improve efficiency. The common-gate transistor of output stage adopts self-biased technique which prevents the transistor from being broken down. Driver stage consists of Class-E, which turns the transistor of output stage on and off more efficiently. The network is used to improve overlap of current and voltage of output stage. By employing these techniques,the power amplifier can deliver 23. 44 dBm output power at 2. 4 GHz with 58. 99% power added efficiency at 2. 8-v supply.

关 键 词：PAE Class-E功率放大器 输出级 驱动级 

分 类 号：TN722[电子电信—电路与系统]