高速信号采集处理电路时钟网络分析与设计  

Analysis and Design of Clock Network for High-Speed Signal Acquisition and Processing Circuit

作　　者：魏振[1] 孙垂强[1] 李栋[1] 

机构地区：[1]中国空间技术研究院西安分院,西安710000

出　　处：《空间电子技术》2016年第6期59-62,共4页Space Electronic Technology

摘　　要：时钟网络可实现时钟产生、恢复、抖动滤除,频率合成和转换、分发和驱动等功能。时钟网络在高速信号采集处理电路中起着至关重要的作用。该部分设计的好坏直接影响产品的性能,甚至功能能否实现。首先将时钟芯片按照功能进行了区分,分析了几种时钟接口匹配方式,然后设计了一种时钟网络,经过仿真和测试,电路各项指标均满足设计要求,证明时钟分配网络性能优异。借鉴该方法,选择合适的芯片,能满足目前多数高速信号采集处理电路的设计需求。Clock network can be used to clock generation and recovery,jitter remove,frequency synthesis and conver-sion,clock distribution and drive.Clock network plays a crucial role for high-speed signal acquisition and processing circuit.The design of clock network directly influences the performance of products,even the realization of the function.First,theclock chips were classified according to the function,and several interface matching methods were analyzed. Then,a newclock network was designed.The simulation and test results show that the proposed clock network can provide excellent per-formance.By this method,almost requirements can be met with the appropriate chip.

关 键 词：高速信号 采集处理电路 时钟网络 

分 类 号：V443[航空宇航科学与技术—飞行器设计]