基于杂散电感分析的MOSFET模块布局结构设计的研究  

Study of MOSFET Module Layout Structure Design Based on Analysis of Stray Inductance

作　　者：代茜[1,2] 徐菊[1] 郑利兵[1] 靳鹏云[1] 

机构地区：[1]中国科学院电工研究所,北京100190 [2]中国科学院大学,北京100049

出　　处：《现代科学仪器》2016年第6期68-72,共5页Modern Scientific Instruments

摘　　要：金属氧化物半导体场效应晶体管（Metal—Oxide—Semiconductor Field-Effect Transistor,MOSFET）模块内部芯片布局及封装结构的不同引起的寄生电感分布的差异对模块的可靠性有直接的影响。为了减小模块内部的杂散电感，提高模块工作的可靠性，本文提出了三种符合要求的功率模块芯片布局结构，对比分析了功率模块内部三种芯片布局结构产生的环路寄生电感对开关过程的影响。结果表明通过不同的布局结构设计，可以实现减小杂散电感，提高模块工作可靠性的目的，为模块的封装提供参考。Different metal oxide semiconductor field effect transistormodulehas different parasitic inductance distribution, which is caused by internal chip layout and packaging structure, parasitic inductancehas the direct impact on the reliability of the module. In order to reduce the stray inductance in the module and improve the reliability of the module, three kinds of power modules was proposed in this paper.The influence of the circuit parasitic inductance generated by the three chip layout structure on the switching process was compared and analyzed. The resultsshowed that the layout of different structure design can reduce the stray inductance and improve the work reliability of the module. It can provide the reference for the module package

关 键 词：MOSFET功率模块 芯片布局 双脉冲测试 开关损耗 杂散参数 有限元 

分 类 号：O657.63[理学—分析化学]