非规则串行程序隐式线程级推测并行发展综述  

Survey of implicit thread-level speculation parallel technology for irregular serial programs

作　　者：李远成[1] 刘斌[2] 

机构地区：[1]西安科技大学计算机科学与技术学院,陕西西安710054 [2]西北农林科技大学信息工程学院,陕西杨凌712100

出　　处：《西安邮电大学学报》2017年第1期99-105,共7页Journal of Xi’an University of Posts and Telecommunications

基　　金：陕西省教育厅科学研究计划资助项目(2013JK1187);中央高校基本科研业务费专项资金资助项目(2452015194)

摘　　要：基于片上多核处理器体系结构,概述在非规则串行程序自动并行化领域中,隐式线程级推测并行技术的特点、研究现状、以及所面临的挑战。从程序特征分析、多线程划分、软硬件协同加速方法和性能功耗评估等4个方面,探讨线程级推测技术未来的发展趋势和研究方向。Based on the system structure of chip multiprocessor（CMP）,the development and research status,characteristics and challenges of implicit TLS parallel technology in the field of automatic parallelization of the traditional irregular serial program are reviewed in this paper.A thorough and detailed analysis are conducted on four aspects of the TLS technique,namely program feature analysis,multi-thread partitioning,accelerating method based on hardware and software co-design,and performance and power consumption evaluation.Directions of TLS technology in the future development and some possible research ideas are also presented.

关 键 词：线程级推测 自动化并行 片上多核处理器 软硬件协同设计 非规则程序 

分 类 号：TP393.07[自动化与计算机技术—计算机应用技术]