基于FPGA时域有限差分算法的设计与实现  

An FPGA Implementation of Finite Difference Time Domain Algorithm

作　　者：赵倩[1] 

机构地区：[1]上海电力学院电子与信息工程学院,上海200090

出　　处：《上海电力学院学报》2017年第1期69-72,96,共5页Journal of Shanghai University of Electric Power

摘　　要：以时域有限差分法的二维形式为例,用Verilog HDL语言加以实现.采用32位单精度浮点数进行加减法和乘法运算,以保证计算的精度.通过modelsim软件仿真,以Altera FPGA的硬件实现来确保设计的正确性.实验结果显示,基于FPGA的时域有限差分法硬件实现方法对提高速度效果明显,是提高算法性能的有效途径.Finite difference time Domain algorithm is a popular algorithm in the computation e- lectromagnetic. However, the huge computing capacity is a limiting factor for its applications. This paper presents implementation of the 2D FDTD algorithm by FPGA whose circuit is described by the verilog HDL. 32 Bit single-precision floating-point specification is adopted to ensure the accu- racy of calculation. After the Modelsim software simulation, the correctness of the design is ensured by the hardware implementation of Altera FPGA. The experimental results show that FPGA imple- mentation speeds up the algorithm greatly. Thus, it becomes an effective way to improve the per- formance of FDTD algorithm.

关 键 词：时域有限差分法 可编程逻辑器件 VERILOG硬件描述语言 二维TM波 

分 类 号：TN791[电子电信—电路与系统]