基于双线性插值算法的缩放IP核设计  

Scaler IP Core Design Based on Bilinear Interpolation Algorithm

作　　者：邹学瑜 刘昌禄[1] 胡敬营[1] ZOU Xue-yu LIU Chang-lu HU Jing-ying(Jiangsu Automation Research Insititute,Liangyungang,Jiangsu 222006,Chin)

机构地区：[1]江苏自动化研究所,连云港222006

出　　处：《计算技术与自动化》2017年第1期113-117,共5页Computing Technology and Automation

摘　　要：设计了基于双线性插值算法的IP核,通过减少乘法器数量,优化了对该算法的实现。针对一般的双行缓冲器不能满足高实时显示要求,及帧存储器成本高且还需另外进行帧存储器的控制逻辑设计的缺点,设计了一个RAM FIFO的缓冲阵列,利用多个RAM存储器保证图像数据存储和时序性控制,它能够有效进行数据缓冲。最后给出了设计的时序仿真,进行结果验证后得到缩放的图像质量较好。通过和已有IP核进行对比,得出绝对平均误差非常小。This thesis designed an IP core based on bilinear interpolation algorithm. By decreasing the number of multi- plers, this design optimized the implementation of the algorithm. The general two line buffer has the following drawbacks： not satisfying the quest of high real-time quality, high cost of frame memory and need of logic control for frame memory. So, this thesis designed a data buffer array called RAM FIFO. This thesis used multiple RAM to ensure the control of timeordered and to save correctly the data of picture, which can make the data buffer more effective. At last, the time--ordered simulation of the design and the test result were introduced. The quality of resizing pictures is good. Comparing this IP core with the existed one, the Mean Absolute Error is very small.

关 键 词：图像缩放 SCALER IP核 双线性插值算法 RAM FIFO 

分 类 号：TN911.73[电子电信—通信与信息系统]