ARM+FPGA的双模导航接收机硬件平台设计  

Hardware Platform Design of Dual-mode Navigation Receiver Based on ARM+FPGA

作　　者：刘宁[1] 马洪涛[1] 王晓君[1] 

机构地区：[1]河北科技大学信息科学与工程学院,石家庄050000

出　　处：《单片机与嵌入式系统应用》2017年第4期21-23,共3页Microcontrollers & Embedded Systems

摘　　要：卫星导航系统能够为广大用户提供全天时、全天候、高精度的导航、定位和授时服务。本文介绍一种基于ARM+FPGA架构的GPS/BDS双模导航接收机的设计方法。该设计分为3部分:射频部分电路设计、FPGA部分电路设计和ARM电路设计。其中,射频部分主要完成GPS/L1频点、BD2/B1以及B3频点卫星信号的下变频及采样。FPGA部分做信号处理,ARM负责信息处理。经过测试,此设计是可行的,能够达到导航接收机对于定位和授时精度的要求。The satellite navigation system is able to provide the broad masses of users throughout the day, all-weather, high precision of the navigation, positioning and timing services. In the paper,a design scheme and implementation of GPS/BDS dual-mode navigation receiver based on ARM＋FPGA is introduced. The design is divided into three parts, such as the radio frequency circuit design, FPGA and ARM circuit design. The satellite signal of GPS L1 and BD2 B1 and B3 frequency point is amplified,down-converted and sampled by the radio frequency circuit. The signal is processed by the FPGA and the information is processed by ARM. The experiment results show that the design is feasible, and it can meet the accuracy requirement of the navigation receiver for positioning and timing.

关 键 词：导航接收机 ARM FPGA 信号 

分 类 号：TN965.5[电子电信—信号与信息处理]