基于Verilog的模拟前端时序的实现方法  

Implement of Analog Front end Timing by Verilog

作　　者：赵地[1] 朱兴华[1] 孙辉[1] 杨定宇[1] 王进[1] 李小辉[1] 

机构地区：[1]成都信息工程大学光电技术学院,四川成都610225

出　　处：《电子科技》2017年第4期144-147,共4页Electronic Science and Technology

基　　金：四川省科技支撑计划基金资助项目(2014GZ0020;2014GZX0012;2015GZ0194;15ZB0173;2016FZ0018)

摘　　要：针对如何高精度、高速实现模拟前端时序的问题,提出了一种用于平板探测器的模拟前端时序的Verilog实现方法。Verilog语言的编程整体上采用模块化设计,主要包含电荷采集模块、数据读出模块和计数器模块。利用锁相环技术设置各模块不同的时钟信号,通过编写有限状态机和改进型计数器实现各模块的时序。仿真结果表明,该编程方法满足了时序高精度实现的需求,具有运行速度快、灵活性高等特点,达到了预期效果。A method of Verilog realization of the analog front end timing used in the flat panel detector is proposed for the implement with high precision and high speed of analog front end timing. Verilog programming uses of modular design including charge collection module,data reading module and counter module on the whole. Each module is set different clock signal by phase locked loop technique,and achieved by writing finite state machine and improved counter. The simulation results show that the method meets the requirements of realizing the timing with high precision,and achieves the desired effect with fast speed and high flexibility.

关 键 词：平板探测器 模拟前端 时序 VERILOG 仿真 

分 类 号：TP311.1[自动化与计算机技术—计算机软件与理论]