功率VDMOS器件中纵向电场的研究  

Research electric field on the vertical direction of Power VDMOS design

作　　者：任向兵 鲍嘉明[1] 宁可庆[1] 

机构地区：[1]北方工业大学电子信息工程学院微电子系,北京100144

出　　处：《电子设计工程》2017年第8期83-86,共4页Electronic Design Engineering

摘　　要：本课题的研究目的旨在从改变功率VDMOS的结构参数入手得到外延层厚度和栅源电压对功率VDMOS纵向电场的影响,并且在结构参数变化的范围内分析出最大电场位置的变化,为优化器件的性能起到指导作用。通过二维仿真工具TSUPREM4和MEDICI仿真器件的结构和电场并以图表的形式计算得到最大电场位置的变化趋势。通过修改器件的外延层厚度得到了在不同的参数下其纵向电场的分布接近封闭的拱形曲线并且随着外延层厚度的增加最大电场的位置接近线性的变化趋势,外延层厚度每增加1.5um到2.5um,最大电场点的位置会上升外延层厚度的百分之3到百分之6。改变器件的栅源电压使器件在进入准饱和区之后纵向电场分布十分稳定不在受栅源电压的影响而没有进入准饱和区时电场随着栅源电压的增大而增大。This research purpose is that change the structural parameters epitaxial layer thickness and gate source voltage of the power VDMOS then get the tendency of the electric field on the vertical direction. Then analysis the change of maximum electric field position within the scope of the structural parameter , in order to optimize the device performance and play a guiding role. Through the two- dimensional simulation tools TSUPREM4 and MEDICI simulated device＇s structure and electric field in the form of chart and calculated the change of the maximum electric field position. By changed the device epitaxial layer thickness that under different parameters the electric field on the vertical direction distributed near closed arch and epitaxial layer thickness increased, the location of the maximum electric field changed close to linear trend. Change device gate source voltage after entered the quasi saturation zone electric field on vertical direction is very stable and does not affected by the gate source voltage, if device is not entering the quasi saturation zone the electric field is increase by the gate source voltage rise.

关 键 词：纵向电场 外延层厚度 栅源电压 准饱和效应 

分 类 号：TN4[电子电信—微电子学与固体电子学]