基于FPGA的线阵型CCD驱动电路设计  

Driving Circuit Designing of Linear Array CCD Based on FPGA

作　　者：程瑶[1] 周娜[1] 王荣秀[2] 

机构地区：[1]重庆理工大学机械工程学院,重庆400050 [2]重庆工商大学,重庆400067

出　　处：《电子器件》2017年第1期82-86,共5页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(51505052;51505053);重庆市科委基础与前沿研究一般项目(cstc2016jcyj A0497);重庆市教委科学技术研究项目(KJ1500935;KJ1500931;KJ1500617)

摘　　要：CCD驱动电路的设计是实现CCD各种设计功能的关键性因素,只有对其驱动信号设计的严格把关,才会进一步保证CCD器件后续工作的开展。分析线阵CCD器件TCD1703C的驱动时序要求,采用QuartusⅡ软件,选用Verilog HDL语言设计了各路驱动时序信号。将程序设计下载到FPGA器件中,通过逻辑分析仪对输出信号进行了波形监测,验证了线阵CCD的驱动时序设计的可行性。将产生的驱动时序信号接入CCD器件,不同光照入射的条件下,CCD在驱动信号的驱动下,正常工作并输出了相应的视频信号。The design of driving circuits is a crucial factor to realize the various design features.Only with the strict driving signals desiging,the CCD devices can perform the further work.The TCD1703C driver timing requirements for linear array CCD device were analyzed. And the driving signals were designed by using Quartus Ⅱ software and Verilog HDL. The program was downloaded to the FPGA device, and the output signals＇ waveforms were monitored by the logic analyzer. So the feasibility of the time sequence design of linear array CCD was verified. Finally, connecting the driving signals to the CCD device, the CCD was driven by the driving video signal was output under the different illumination conditions. signals, and the corresponding

关 键 词：CCD 驱动电路 FPGA QuartusⅡ VERILOG HDL 

分 类 号：TN386.5[电子电信—物理电子学]