双核SoC芯片扫描链测试设计与实现  

Design and Implementation of Scan Based Test for Dual-core SoC

作　　者：刘广东[1] 石国帅 徐浩然[1] 

机构地区：[1]北京计算机技术及应用研究所,北京100854

出　　处：《计算机测量与控制》2017年第4期15-17,33,共4页Computer Measurement &Control

摘　　要：针对芯片生产过程中可能引入短路和断路等制造缺陷的问题,实现了基于扫描链测试的双核SoC芯片可测性设计电路;根据双核SoC中DSP硬核、CPU软核特点采用不同的扫描链设计方案:利用DSP硬核中已有扫描链结构,将DSP测试端口复用到芯片顶层端口,在CPU软核和其它硬件逻辑中插入新的扫描链电路;扫描链测试支持固定型故障测试和时延相关故障测试;针对时延故障测试,设计了片上时钟控制电路,利用PLL输出高速时钟脉冲进行实速测试;采用自动测试向量生成工具产生测试向量,结果表明,芯片固定型故障的测试覆盖率可以达到97.6%,时延故障测试覆盖率可以达到84.9%,满足芯片测试覆盖率要求。In order to detect the defect of manufacturing such as short and open circuit, the scan based DFT circuit of dual core SoC is realized. The scan structure has been inserted into the hard-core DSP, so the DSP＇ s test ports are connected to the SoC chip leads. Scan chains are inserted into the CPU core and other hardware logic. Scan based test supports stuck-at fault and transition fault test. According to the transition fault, an on-chip clock control circuit is designed to use high speed PLL clock for at-speed test. The ATPG tool is used to generate test vectors, the result shows that the stuck-at fault test coverage rate can reach 97. 6%, transition fault test coverage rate can reach 84.9 %, meet the test coverage requirements of the chip.

关 键 词：可测性设计 扫描链测试 双核 片上时钟控制 

分 类 号：TN407[电子电信—微电子学与固体电子学]