一种HEVC标准中IDCT变换的FPGA实现  

An IDCT transform implementation on FPGA in HEVC

作　　者：黄友文[1] 董洋[1] 

机构地区：[1]江西理工大学信息工程学院,江西赣州341000

出　　处：《电子技术应用》2017年第5期38-40,共3页Application of Electronic Technique

基　　金：江西省教育厅科技项目资助(GJJ150683);江西理工大学校级重点课题资助(NSFJ2014-K18)

摘　　要：为降低新一代高效视频编码(HEVC)标准中解码端多尺寸逆离散余弦变换(Inverse Discrete Cosine Transform,IDCT)中的资源消耗,设计了一种IDCT硬件电路结构。通过使用现场可编程门阵列(Field-Programmable Gate Array,FPGA)内部嵌入式RAM单元进行矩阵转置运算,从而减少了对内部寄存器的使用。对IDCT系数矩阵进行分解得到不同尺寸下的统一运算电路结构,利用流水线技术实现对运算单元的加速,同时采用并行数据调度减少数据处理等待时间。设计结果表明,设计吞吐量为3.6点/时钟周期,满足了4k×2k@30 f/s视频信号的实时处理需求。To reduce the mutl-sized II）CT resource consume in the decoder of the new generation HEVC（High Efficient Video Coding）, an IDCT processing circuit was proposed.In order to reduce the using of inner registers ,the embedded RAM units in FPGA were used to process the matrix transposition. A uniform circuit architecture of IDCT was derived from the decomposition of coefficient matrix.Pipeline technology was used to speed up the operation.Meanwhile,parallel data schedule will help to reduce the processing latency. Result showed that the throuput is 3.6 points per clock.It can handle 4k×2k@30 f/s video signal.

关 键 词：HEVC IDCT FPGA 嵌入式RAM 

分 类 号：TN919.81[电子电信—通信与信息系统]