无线通信接收机位同步时钟提取电路设计  

Design of Bit Synchronization Clock Extraction Circuit for Wireless Communication Receiver

作　　者：林彬彬[1] 施隆照[1] 陆培民[1] 

机构地区：[1]福州大学物理与信息工程学院,福建福州350116

出　　处：《电子技术（上海）》2017年第4期36-39,共4页Electronic Technology

摘　　要：介绍了一种采用数字锁相法实现快速位同步时钟提取的设计方案。设计应用于无线通信接收机中,对解调得到的数字基带信号进行时钟恢复,以实现数据码元的正确采样判决。该方案以超前-滞后型锁相环为基础并进行适当改进,根据用于产生位同步时钟的分频器的计数值来决定每次相位调整的步长,仅需一次便可完成相位的跟踪锁定,极大地提高了位同步速度;同时设计对输入信号也进行了必要的滤波处理,进一步增强了其抗干扰性能。通过一系列的仿真验证,证明了只要每次相位调整时累积相位误差小于码元位宽的50%,该设计均可实现正确同步。This paper introduces a kind of design method of fast bit synchronization clock extraction based on Digital Phase-Locked Loop（DPLL）. The design is used in the wireless communication receiver to recover the clock of demodulated digital baseband signal in order to realize the correct sampling and judgment of the data symbols. The scheme makes some appropriate improvements on the basis of lead-lag DPLL（LL-DPLL）. The step size of each phase adjustment is determined according to the count value of the divider which is used to generate the bit synchronization clock. The phase locking can be completed within a single adjustment, which greatly improves the speed of bit synchronization. Moreover, the input signal is properly filtered to further enhance the anti-jamming performance.Through a series of simulations and verifications, it is proved that the design can achieve the synchronization correctly as long as the cumulative phase error for each phase adjustment is less than 50% of the bit width.

关 键 词：位同步 数字锁相环 无线接收机 

分 类 号：TN402[电子电信—微电子学与固体电子学]