基于扫描链修改的低功耗测试方案  

Low power test scheme based on scan chain modification

作　　者：张培明[1] 商进[2] 李晓龙[1] ZHANG Peiming SHANG Jin LI Xiaolong(College of Electrical and Information Engineering, Heilongjiang of Institute of Technology, Harbin 150050,China Control Technology Institute, Wuxi Institute of Technology, Wuxi 214121, China)

机构地区：[1]黑龙江工程学院电气与信息工程学院,黑龙江哈尔滨150050 [2]无锡职业技术学院控制技术学院,江苏无锡214121

出　　处：《黑龙江工程学院学报》2017年第2期45-48,共4页Journal of Heilongjiang Institute of Technology

基　　金：黑龙江省教育厅科学技术研究项目(12531565)

摘　　要：芯片测试过程中存在的高功耗问题是制约芯片测试发展的难题,针对此问题,提出一种新的低功耗测试方法。该方法通过插入异或门,将扫描链中的部分D触发器用T触发器代替,同时采用遗传算法对测试结构进行修改和测试向量重排序,为了保证故障覆盖率和故障仿真的正确性,对测试数据进行转换,从而降低由于节点电压跳变所导致的电平翻转次数,达到降低测试功耗的目的。根据部分ISCSAS 89基准电路的实验结果表明:该方法符合预期目标,平均功耗相对于未采用该方法前降低51.26%。Aiming at the problem of high power consumption during the test of the chip,this paper presents a low power test method based on testability design.By inserting the XOR gate,part Dflip-flop of scan chain is replaced by using Tflip flops,and genetic algorithm is used to the test structure to modify and test vector reordering.In order to ensure the correctness of the fault coverage and fault simulation,test data is transformed,so that the frequency of the voltage change caused by the node voltage is reduced,and purpose of reducing the power consumption is achieved.Experimental results based on some IS89 benchmark circuits shows that the proposed method can reduce the power consumption,and the average power consumption reduction ratio is 51.26%.

关 键 词：扫描链 测试向量重排序 遗传算法 低功耗测试 

分 类 号：TP391.46[自动化与计算机技术—计算机应用技术]