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作 者:周雅[1]
机构地区:[1]许昌学院电气(机电)工程学院,河南许昌461000
出 处:《半导体技术》2017年第5期335-339,399,共6页Semiconductor Technology
基 金:河南省教育厅科学技术研究重点项目(16A413013);河南省科技攻关项目(172102210465);许昌市科技发展计划项目(1502094);许昌学院优秀青年骨干教师资助项目
摘 要:提出了一种基于负阻退化技术的2.4 GHz高线性亚阈值混频器,该混频器相对于传统结构而言,增加了两个交叉耦合电容。由于该结构的内部负阻退化技术抵消了寄生电容,因而降低了寄生电容对增益和线性度的影响,改善了增益和线性度。采用基于Volterra级数的小信号模型,分析交叉耦合电容对于输入三阶交调点IIP_3和增益的影响。分析表明该方法确实能够改善IIP_3性能。采用TSMC 0.13μm CMOS工艺进行设计并流片,该芯片大小为0.22 mm×0.2 mm。芯片测试结果表明,该混频器在2.1 mW功耗的情况下,获得了13.4 dB的增益,并且IIP_3高达5.4 dBm。A 2.4 GHz high-linearity subthreshold mixer based on a negative impedance degeneration technology was presented. Compared with the traditional structure, the mixer was formed by adding two cross-coupling capacitors. Since the parasitic capacitance was offset by the internal negative impedance degeneration technology, the influences of the parasitic capacitance on the gain and linearity were alleviated, so that the gain and linearity were improved. Small-signal model calculations with Voherra series were adopted to analyze the effects of the cross-coupling capacitors on the input third-order intercept point IIP3 and gain, confirming that the IIP3 performance can be improved by this design approach. The mixer was designed and implemented using TSMC 0.13 μm CMOS technology with a chip area of 0.22 mm× 0.2 mm. The test results show that a conversion gain of 13.4 dB and an IIP3 of 5.4 dBm can be achieved with a power consumption of 2.1 mW of the mixer.
分 类 号:TN432[电子电信—微电子学与固体电子学] TN773
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