异步时钟域信号同步的实现  

Implementation of asynchronous clock domain signal synchronization

作　　者：金大超[1] 冷建伟[1] 

机构地区：[1]天津理工大学自动化学院,天津300384

出　　处：《天津理工大学学报》2017年第3期40-44,共5页Journal of Tianjin University of Technology

摘　　要：随着数字电子系统设计的快速发展,FPGA(现场可编程门阵列)在一些实际应用系统中通常包含有多个不同时钟,而系统功能实现的前提就是要完成数据在多个不同的时钟域之间进行传输,通常会产生亚稳态危害,为了较小亚稳态风险,本文分析了在跨时钟域时系统可能出现的亚稳态问题,提出了在FPGA工程设计中实现不同时钟域间的数据同步方法,对异步FIFO缓存法做了重点介绍.读写地址指针均采用了格雷码的形式,格雷码的特点是的相邻元之间每一次只有一位数据发生变化,所以系统的亚稳态风险会减小,通过Modelsim软件的仿真,验证了异步FIFO的应用可以有效的解决数据的跨时钟域传输问题.With the rapid development of digital electronic system design, FPGA （field programmable gate array ） in some of the practical application of the system usually contains many different clock, and the premise of the realization of the system function is to complete the transmission of data between different clock domains,usually make the metastable harm.For reducing the risk of metastable, In this paper, we analyze the problem of sub steady state when the system is in time domain, and propose the method of data synchronization between different clock domains in FPGA engineering design. Read and write address pointer using the gray code and gray code is adjacent to the yuan each time only one bit of data changes, so the system of metastable risk will decrease. Finally, we by Modelsim software simulation to verify the asynchronous FIFO application can effectively solve the data of cross clock domain transfer problem.

关 键 词：FPGA(现场可编程门阵列) 异步FIFO 跨时钟域 亚稳态 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]