基于现场可编程门阵列的高斯滤波算法优化实现  

Optimizing implementation of Gaussian filter based on field programmable gate array

作　　者：陈超[1] 罗小华[1] 陈淑群[1] 俞国军 CHEN Chao LUO Xiao-hua CHEN Shu-qun YU Guo-jun(College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China Spreadtrum Technology（Hangzhou） limited company, Hangzhou 310052, China)

机构地区：[1]浙江大学电气工程学院,浙江杭州310027 [2]展讯科技(杭州)有限公司,浙江杭州310052

出　　处：《浙江大学学报（工学版）》2017年第5期969-975,共7页Journal of Zhejiang University：Engineering Science

基　　金：国家"863"高技术研究发展计划资助项目(2012AA041701)

摘　　要：针对传统高斯滤波算法硬件设计方法中关键路径较长、逻辑延时较大的问题,提出加数压缩的硬件优化实现方法.在高斯滤波算法优化实现过程中,采用移位操作来实现乘法与除法计算,避免使用乘法器与除法器.并引入保留进位加法器(CSA)、基于多路选择器(MUX)的4-2压缩器、加数压缩的树型结构,对9个加数进行3个层次的压缩.经过优化后,只需1个全加器便可得求和结果.结果表明,经过加数压缩设计可以达到缩短关键路径、减少逻辑延时的目标,使逻辑延时缩小32.48%,同时还极大节省所需加法器宏单元数,为后续图像处理模块提供更大的设计自由度.A hardware optimizing implementation with compressing attends was proposed for the problemthat the critical path of traditional Gaussian filter hardware implementation is long and the logic delay islarge. In the Gaussian filter hardware optimizing implementation process, shift operation was used toachieve multiplication and division calculation in order to avoid the use of multipliers and dividers. Threekinds of circuit structure, i. e. Carry Save Adder （CSA）, 4-2 compressor based on two multiplexer（MUX）, and tree structure for compressing attends, were used to compress the nine attends at threelevels. After optimizing, only one full adder was needed to obtain the sum of results. The experimentalresults show that the hardware optimizing implementation of Gaussian filter with compressing attends canshorten the critial path and reduce the logic delay. The proposed method reduces the logic delay by32.48% and occupies less Macro Statistics of Adders compared with the traditional implementation. Thesaved Macro Statistics of Adders can provide greater design freedom for the following image processing units.

关 键 词：高斯滤波器 保留进位加法器 基于MUX的4-2压缩器 加数压缩的树型结构 全加器 

分 类 号：TN47[电子电信—微电子学与固体电子学]